Save power and real estate with a programmable reset controller with debounced input

The frequent deployment of hard reset functions on devices such as GPS units, PDA's, modems, set-top boxes and other devices (requiring complete system reboot from such anomalies as line outages) often use a simple pushbutton interface. This interface initiates a long time-delay pulse whereby re-initialization can both begin and remain uninterrupted until the task is complete.

For reasons relating to security or to the required reboot time, the pushbutton may need to be depressed for as long as some tens of seconds. An intelligent timer integrated into the system is used to ensure the pushbutton is depressed for some minimum, albeit lengthy time, known only to the service person performing the reboot.

The use of the low-cost single pole, single throw pushbutton requires a de-bounce circuit to ignore false triggers from an unintended closure and the multiple switch closures resulting from pushbutton bounce. Mercury-wetted switches once considered a remedy for the simple pushbutton bounce nuisance, are rarely used as a switch bounce remedy due to cost and impact on the environment.

A simple mono-stable multivibrator or one-shot, used with a logic gate discriminates from pulses of too short a duration. By choosing the one-shot pulse-width greater than the duration of the switch bounce pulse duration it also rids the receiving circuit of the multiple pulses from the pushbutton. Additionally, it can be used to ignore false trips by adjusting the pulse width (for example, into the hundreds of millisecond range).

As a low cost solution, the 555 timer or one of its many variants works well in this application using medium range valued components for the R-C time constant circuit thus keeping cost down. As shown in Figure 1a, the one-shot generates a pulse each time the pushbutton is depressed. If the length of the pulse from the pushbutton is less than the one-shot, the logic gate does not allow the pulse to pass. When the pulse equals or exceed the preset pulse width, the gate outputs a pulse equaling the difference of the pushbutton closure time minus the one-shot's chosen pulse width.

The addition of another one-shot and logic gate (Figure 1b) adds the long time delay reset pulse feature, which is activated once a pulse is output from the debounce circuit, and is not valid until the time delay of the second one-shot is equaled or exceeded. Although a single one-shot plus logic gate can serve the purpose of switch debounce, the addition of the second pulse discriminator allows the first to act as a short time delay reset pulse generator or "Soft Reset" generator and the second acts as the long time constant system reboot pulse generator or "Hard Reset".

Figure 1b: Addition of One-Shot and Logic Makes a Dual Pulse Discriminating Timer (One Shot, One Long)

It is the long time delay of the Hard Reset that poses the design problem as delays into the tens of seconds call for very large value resistors and capacitors to implement this function. Assuming a delay of 25 seconds is required and choosing a 10MΩ resistor yields a required capacitor value of 2.3μF and we choose the standard value 2.2μF for this circuit. For reliable operation across temperature a type X7R ceramic is used which has relatively low leakage current and is fairly stable in capacitance value change versus temperature. The shorter time constant required of the "Soft Reset" one-shot alleviates the demand on the higher value resistor and capacitor but not on the capacitor type. The X7R type dielectric is the right choice for this circuit.

Figure 2: Dedicated Reset Controller with Debounced Input, Programmable Timers and Voltage Monitor

Although this analog solution is both simple and low cost it lacks flexibility and accuracy. Should system reset requirements change, units in the field must be physically reworked to make adjustments to the either of the two timers. A software solution is attractive in that it can easily be reprogrammed to meet system changes without necessitating hardware changes.
Microprocessor example
A microprocessor based timer permits changes to be made as required without the need for dismantling the system to adjust or replace resistors or capacitors and adds accuracy from its crystal oscillator derived clock. Ideally, the system uses a microprocessor that can be adapted to this task by some modification of code and the availability of an unused input port or interrupt pin. If the on-board micro is not up to the task a microcontroller or low-level microprocessor can serve this function but not without adding significant cost not to mention PCB space and support circuitry such as the crystal oscillator.

A low pin count, programmable reset controller with debounced pushbutton input interface and supply voltage monitor alleviates the cost issue associated with the microprocessor solution while maintaining the programmability and accuracy edge of the microprocessor and the simplicity of the analog solution (see Figure 3).

Figure 3: Timing Diagram of Programmable Reset Timer

For example, employing a 15μs debounced contact closure input, the Summit SMR101 contains the circuitry to generate a reset pulse from a short depression of the pushbutton; a "Soft Reset", and a separate "Hard Reset" pulse the result of holding down the pushbutton longer then the pre-programmed time delay. Once the pushbutton closure is sensed both the Soft and Hard reset timers are enabled and after their respective delays are reached the respective output goes low for as long as the pushbutton is held low, remaining low until the pushbutton is released and returning high after a programmed delay time of 1ms to 200ms.

The heart of the delay timers is the reasonably accurate (±10%) 8kHz ring oscillator. The oscillator provides a count pulse for the binary counter that is programmable in eight increments for both the short or Soft Delay and the Hard Delay. The debounced pushbutton input contains its own pullup resistor to VDD, eliminating yet another component from the final circuit. The Soft Reset is provided another trigger input; that of the VDD supply voltage. Divided down by user inputted data, the VDD voltage is compared against an internal reference and when this reference voltage is exceed the comparator output is passed through a 15μs glitch filter to prevent spurious triggering of the Soft Reset output where it acts on the Soft Reset output just as the pushbutton input does.

The flexibility of the SMR101 comes from its on-board user configurable EEPROM where changes to any of the timers' delay times or the VDD trip point can be readily made through a simple proprietary interface. Changes to any of these settings can be made "on the fly" and will be retained after the device loses power. When system requirements make necessary changes to the timer intervals or even the VDD trip point the programmability feature allows for such changes simply and quickly, in the factory or in the field.
A closer look at the interaction of the pushbutton, voltage on VDD and the timer output states are shown in Figure 4. Upon application of power to VDD above the undervoltage set point (wave 1), the comparator detects a valid supply voltage and after 15μs of validity the reset timer is started and after the timeout interval, the Soft Reset# output goes high. If at any time during valid operation a voltage glitch of 15μs or greater is experienced on VDD, the Reset timer will be re-triggered, asserting the SOFT_RESET# output until after the glitch has disappeared plus the Reset delay time. Note that the HARD_RESET# output is unaffected by the undervoltage condition occurring on VDD.

Figure 4: Windows GUI Display of Programmable Reset Timer Configurable Settings

Next, the pushbutton is depressed for an interval of time greater than the preprogrammed Soft Reset time of 250ms but less than the preprogrammed Hard Reset time of 4 seconds. Once the button is depressed for ≥250mS, the SOFT_RESET# output is asserted and remains asserted until the pushbutton is released; returning high T_RESET (100ms) after the pushbutton is released. As the pushbutton was not held down for the programmed Hard Reset time, the HARD_RESET# output was not asserted.

By holding the pushbutton down for the full duration (≥4 seconds) of the preprogrammed Hard Reset time, both the SOFT_RESET# and HARD_RESET# outputs will be asserted. The duration of the SOFT_RESET assertion time is the pushbutton closure time minus the Soft Reset programmed time plus the Reset Timeout Period or t_PB − t_SR + t_RESET. The duration of the Hard Reset assertion time will be the pushbutton closure time minus the Hard Reset programmed time plus the Reset Timeout Period or t_PB − t_HR + t_RESET.

Programming the Reset Controller requires only a Personal Computer with a Windows Operating System and the SMR101 GUI software loaded. In Figure 4 it is shown the Reset Timer programmed to 100ms, the Soft Reset Timer to 250ms and the Hard Reset Timer to 4 Seconds. In this example, after the pushbutton is depressed for 100ms, the SOFT_RESET# output is asserted and holding the pushbutton closed for a total of 4 seconds also asserts the HARD_RESET# output. Assuming the button is depressed for 5 seconds, both the Soft and Hard Reset timers will become reasserted 5.1 seconds after the pushbutton was depressed. Setting the programmable reset timer's functions to other values is as simple as checking a selection box to and clicking the "Program" button. The controller commits the new settings to EEPROM after the programming interface has completed its write cycle at 100kHz cycle times.

Conclusion
The benefits of a programmable reset timer becomes obvious when considering long delay times or multiple timers and other features not found on the traditional one shot integrated circuits. Consideration is given to a microprocessor-based design but is discarded when cost is an issue and only the absolute in accuracy is required. A committed programmable controller with reasonable accuracy, minimal parts count and low cost is a sensible solution to many systems requiring a long delay timer. The addition of the on board debounce circuit makes the widely available low cost SPST, normally open pushbutton a perfect fit and accompanying cost advantages. The final advantages, that of a CSP package using only a percentage of a SOT-23 5 pin package and minimal pin count, discourage any look at alternate solutions and allow time for more important undertakings.

About the author
George Hall is Staff Engineer at Summit Microelectronics. He is responsible for supporting customers using Summit devices, evaluation kit design and new product definition. Before joining Summit, Mr. Hall was an applications engineering at Monolithic Power Systems. He has also held positions at Micro Linear Corporation, Micrel Semiconductor, Raynet, Computer Products, and General Electric. Mr. Hall has authored numerous application notes and holds a patent in phase-locking switched-mode power supplies. ghall@summitmicro.com

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